1. Field of the Invention
The present invention relates to a semiconductor integrated circuit that controls, by a switch, connection and disconnection between the internal voltage line of a circuit block and wiring to which a power supply voltage or a reference voltage is applied.
2. Description of the Related Art
MTCMOS (Multi-Threshold Complementary Metal Oxide Semiconductor) technology is known as technology for controlling the shutoff of power supply to a circuit and the cancellation of the shutoff by a switch.
Generally, the threshold voltage of a transistor in a logic circuit or the like needs to be lowered as a design value in order to prevent a signal delay accompanying a decrease in power supply voltage or an element miniaturization. When the threshold voltage of a transistor in a logic circuit or the like is low, a high leakage current occurs. The MTCMOS technology prevents unnecessary consumption of power by a circuit in a stopped state by shutting off a leakage current path of the circuit in the stopped state by means of a transistor (power supply switch) having a higher threshold value than a transistor in a logic circuit or the like.
In application of the MTCMOS technology to a circuit block, internal voltage lines referred to as a so-called virtual VDD line and a so-called virtual GND line are provided within the circuit block. The internal voltage lines are connected to a global real power supply line (real VDD line) and a real reference voltage line (real VSS line) for establishing connection between blocks outside the circuit block, via a power supply switch for power shutoff and the cancellation of the shutoff.
The power supply switch is provided at three kinds of positions, that is, a position between a functional circuit that is started and stopped repeatedly and the real VDD line, a position between the functional circuit and the real VSS line, and both the positions. In general, a PMOS transistor is used as the switch on the VDD side, and an NMOS transistor is used as the switch on the VSS line side.
The starting and stopping of the functional circuit in the MTCMOS applied block is controlled by a circuit in an MTCMOS non-applied block set in an operating state at all times while supplied with power from the real VDD line and the real VSS line after the semiconductor integrated circuit is started. Alternatively, a configuration can be adopted in which a control signal for controlling the starting and stopping of the functional circuit in the MTCMOS applied block can be input from an external terminal of the semiconductor integrated circuit.
A power supply switch can be realized by a cell within an MTCMOS applied block. More specifically, there is a case where within an MTCMOS applied block, a power supply switch is provided in each logic circuit cell of an inverter, a NAND circuit, a NOR circuit or the like, or in a functional circuit cell realized by a few logic circuits, and there is a case where a dedicated power supply switch cell without a logic circuit or a functional circuit is provided. A switch arrangement of this type will hereinafter be referred to as an “internal switch (SW) arrangement,” and a semiconductor integrated circuit adopting the arrangement will hereinafter be referred to as an “internal SW arrangement type IC.”
As opposed to the internal SW arrangement type IC, a semiconductor integrated circuit in which power supply switches are arranged around a circuit block as an object of power supply control is known (see Japanese Patent Laid-Open No. 2003-289245, hereinafter referred to as Patent Document 1 and Japanese Patent Laid-Open No. 2003-158189, hereinafter referred to as Patent Document 2, for example). A switch arrangement of this type will hereinafter be referred to as an “external switch (SW) arrangement,” and a semiconductor integrated circuit adopting the arrangement will hereinafter be referred to as an “external SW arrangement type IC.”
The external SW arrangement is suitably used in combination with a circuit block having a general-purpose circuit (for example a memory, a CPU or the like) referred to as a so-called “macro” as a part or the whole of the circuit block.
Patent Document 2 discloses a configuration in which a transistor cell (switch) is disposed on three sides or four sides of a circuit block, the switches having a shape such that the direction of length of the switches is along the respective sides and the direction of arrangement of a transistor gate line within the switches is the same as the direction of the length.
In this configuration, a VDD supply ring and a VSS supply ring are arranged as an annular line annularly enclosing the periphery of the circuit block on an opposite side (outer side) of a transistor cell arrangement region from the circuit block. The VDD supply ring and the drain of a switch transistor are connected to each other by a metal wiring layer at a level different from that of the VDD supply ring. The VSS supply ring and a VSS line within the circuit block are connected to each other by a metal wiring layer at a level different from that of the VSS supply ring. The source of the switch transistor and a virtual VSS line within the circuit block are connected to each other by a metal wiring layer at a level different from that of the VSS supply ring.